The present invention relates to a waveform generator provided in a mobile communications terminal operable in accordance with a plurality of band limitation characteristics in a modulator for modulating a digital signal.
In recent years, while communications and broadcasts is going digital, the digital modulation technology is essential to correctly transmitting more information. With the advancement of the LSI (Large Scale Integration) technology, features and systems implemented on a plurality of chips in the related art tend to be integrated on a single chip. Under such situations, a shared terminal is in need that supports a plurality of communications systems via a single terminal in the field of mobile communications. While the characteristics of a band limitation filter generally essential to a modulator are specified by the standards of each communications system, such characteristics differ from each other so that it is necessary to provide a waveform generator having a plurality of band limitation characteristics in a shared terminal.
In transmitting a digital signal in a limited band, a roll-off filter is used to prevent interference between digital signals (intersymbol interference) caused by the band limitation filter. A case where band limitation characteristics are different includes a case where the roll-off ratio to determine cut-off characteristics is different or a case where the characteristic function itself is different, such as a Nyquist filter and a route Nyquist filter. FIG. 2A shows the impulse response waveforms (for ±3 symbol cycles) of Nyquist filters with roll-off ratio (α) of 0.5 and 0.25. FIG. 2B shows the impulse response waveforms (for ±3 symbol cycles) of a Nyquist filter and a route Nyquist filter both with roll-off ratio of 0.5. As understood from FIGS. 2A and 2B, the roll-off filter has a property that the center amplitude of an impulse response waveform is around 1 and 0 at the remaining symbol points. This property allows transmission of correct information while suppressing intersymbol interference for an input signal series. FIGS. 3A and 3B show the output waveforms and the difference (difference signal) of the amplitude value between the output waveforms obtained when total seven symbols of a binary signal series {−1, −1, −1, −1, +1, +1, +1} are respectively band-limited using the band limitation characteristics shown in FIGS. 2A and 2B. As understood from FIGS. 3A and 3B, an output waveform band-limited by either band limitation characteristic passes close to the amplitude value of a symbol value input at each symbol point. As a result, the difference signal obtained is much smaller than the amplitude value of each output waveform, even when the band limitation characteristic differs slightly.
The aforementioned roll-off filter may be implemented via a digital filter. Such a digital filter uses a plurality of digital adders so that the resulting circuit scale is larger. Thus, as means for implementing a digital filter via a small circuit scale, a configuration using a ROM (Read-only Memory) is generally used.
A roll-off filter using a ROM performs impulse response according to the band limitation characteristic and convolutional operation of an input signal series in advance, and stores the result in the ROM. The roll-off filter reads data (result of the convolutional operation) from the ROM in accordance with the input signal series and outputs the data as a band-limited signal. Since the operation result according to the band limitation characteristic is stored in the ROM, a plurality of ROMs must be provided in case a roll-off filter having a plurality of band limitation characteristics.
FIG. 9 is a block diagram showing an example of a related art waveform generator operable in accordance with a plurality of band limitation characteristics. In FIG. 9, the waveform generator is provided with a waveform generator 92 having a first band limitation characteristic and a waveform generator 93 having a secondhand limitation characteristic. In case the first band limitation characteristic is requested, the signal series input from an input terminal 91 is supplied to the waveform generator 92 via a selector switch 94. The output from the waveform generator 92 is output as a signal band-limited using the first band limitation characteristic via a selector switch 95 and an output terminal 96. In case the second band limitation characteristic is requested, the selector switches 94 and 95 are changed over. The signal series input from the input terminal 91 is supplied to the waveform generator 93 via the selector switch 94. The output from the waveform generator 93 is output as a signal band-limited using the second band limitation characteristic via the selector switch 95 and the output terminal 96.
FIG. 10 is a block diagram showing a specific exemplary configuration of the waveform generator shown in FIG. 9. This configuration example assumes that the band limitation characteristic, data interpolation ratio in arithmetic operation and bit accuracy of the operation result differ between the first band limitation filter and the second band limitation filter. In FIG. 10, the waveform generator 92 is composed of a counter 101a, an address generator 102a, a ROM 103a as a first band limitation filter, a D/A (digital-to-analog) converter 104a and a post-filter 105a. The waveform generator 93 is composed of a counter 101b, an address generator 102b, a ROM 103b as a second band limitation filter, a D/A (digital-to-analog) converter 104b and a post-filter 105b. 
Next, operation assumed in case the first band limitation characteristic is requested will be described. A signal series having the symbol cycle T input from the input terminal 91 is supplied to a shift register 100 and sequentially shifted in accordance with a clock signal CLK1 (frequency of 1/T). To the address generator 102a are supplied an output from the shift register 100 via the selector switch 94 and an output from the counter 101a for counting a clock signal CLK2 (frequency obtained by multiplying CLK1 by a natural number) corresponding to the data interpolation ratio in the first band limitation characteristic. In the address generator 102a, address data is generated in accordance with an output from the shift register 100 and an output from the counter 101a, and the resulting address data is supplied to a ROM 103a. From the ROM 103a, waveform data stored therein is read in accordance with the supplied address data and output as n-bit digital data (n is a natural number). Accordingly, it is necessary to store waveform data (in nth power of 2) in the ROM 103a. To the D/A converter 104a having a resolution of n bits are supplied digital data from the ROM 103a and the clock signal CLK2. In the D/A converter 104a, digital data supplied from the ROM 103a is converted to an analog signal in the cycle of the clock signal CLK2, and the resulting analog signal is supplied to a post-filter 105a. In the post-filter 105a, an aliasing noise is removed from the supplied analog signal, and the resulting signal is output as a signal band-limited using a first band limitation characteristic via the selector switch 95 and the output terminal 96.
Next, operation assumed in case the second band limitation characteristic is requested will be described. In this case, the selector switches 94 and 95 are changed over. To the address generator 102a are supplied an output from the shift register 100 via the selector switch 94 and an output from the counter 100b for counting a clock signal CLK3 (frequency obtained by multiplying CLK1 by a natural number) corresponding to the data interpolation ratio in the secondhand limitation characteristic. In the address generator 102b, address data is generated in accordance with an output from the shift register 100 and an output from the counter 101b, and supplied to a ROM 103b. From the ROM 103b, waveform data stored therein is read in accordance with the supplied address data and output as m-bit digital data (m is a natural number). Accordingly, it is necessary to store waveform data (in mth power of 2) in the ROM 103b. To the D/A converter 104b having a resolution of m bits are supplied digital data from the ROM 103b and the clock signal CLK3. In the D/A converter 104b, digital data supplied from the ROM 103b is converted to an analog signal in the cycle of the clock signal CLK3, and the resulting analog signal is supplied to a post-filter 105b. In the post-filter 105b, an aliasing noise is removed from the supplied analog signal, and the resulting signal is output as a signal band-limited using a second band limitation characteristic via the selector switch 95 and the output terminal 96.
FIG. 11 is a block diagram showing another specific exemplary configuration of the waveform generator shown in FIG. 9. This configuration example assumes that the data interpolation ratio in arithmetic operation and bit accuracy of the operation result are identical between the first band limitation filter and the second band limitation filter. In FIG. 11, the waveform generator 92 is composed of a counter 101a, an address generator 102a, a ROM 103a as a first band limitation filter, a D/A converter 104a and a post-filter 105a. The waveform generator 93 is composed of a counter 101a, an address generator 102a, a ROM 103b as a second band limitation filter, a D/A converter 104a and a post-filter 105a. That is, the counter 101a, the address generator 102a, the D/A converter 104a and the post-filter 105a are common components of the waveform generators 92 and 93.
Next, operation assumed in case the first band limitation characteristic is requested will be described. The signal series having the symbol cycle T input from the input terminal 91 is supplied to a shift register 100 and sequentially shifted in accordance with a clock signal CLK1 (frequency of 1/T). To the address generator 102a are supplied an output from the shift register 100 via the selector switch 94 and an output from the counter 101a for counting a clock signal CLK2 (frequency obtained by multiplying CLK1 by a natural number) corresponding to the data interpolation ratio. In the address generator 102a, address data is generated in accordance with an output from the shift register 100 and an output from the counter 101a, and supplied to a ROM 103a via a selector switch 94. From the ROM 103a, waveform data stored therein is read in accordance with the supplied address data and output as n-bit digital data (n is a natural number). To the D/A converter 104a having a resolution of n bits are supplied digital data from the ROM 103a via the switch 95 and the clock signal CLK2. In the D/A converter 104a, digital data supplied from the ROM 103a is converted to an analog signal in the cycle of the clock signal CLK2, and the resulting analog signal is supplied to a post-filter 105a. In the post-filter 105a, an aliasing noise is removed from the supplied analog signal, and the resulting signal is output as a signal band-limited using a first band limitation characteristic via the output terminal 96.
Next, operation assumed in case the second band limitation characteristic is requested will be described. In this case, the selector switches 94 and 95 are changed over. Address data from the address generator 102a is supplied to a ROM 103b via the selector switch 94. From the ROM 103b, waveform data stored therein is read in accordance with the supplied address data and output as n-bit digital data. To the D/A converter 104b are supplied digital data from the ROM 103b via the selector switch 95 and the clock signal CLK2. In the D/A converter 104a, digital data supplied from the ROM 103b is converted to an analog signal in the cycle of the clock signal CLK2, and the resulting analog signal is supplied to a post-filter 105b. In the post-filter 105b, an aliasing noise is removed from the supplied analog signal, and the resulting signal is output as a signal band-limited using a second band limitation characteristic via the output terminal 96.
As mentioned earlier, in case the data interpolation ratio in arithmetic operation and bit accuracy of the operation result are identical and only the band limitation characteristic differs between the first band limitation filter and the second band limitation filter, by employing the configuration shown in FIG. 11, it is possible to slightly reduce the circuit scale compared with the circuit shown in FIG. 10. In any way, it is necessary to provide two band limitation filters. Even when such band limitation filters are implemented via ROMs, it is not possible to substantially reduce the circuit scale.